From German Auslegeschrift No. 25 11 518 a method and a circuit arrangement are known for operating an integrated semiconductor store, whose cells consist of flip-flops with bipolar transistors and Schottky diodes as read/write coupling elements. [German Austegeschrift No. 25 11 518 corresponds to U.S. Pat. No. 4,090,255, entitled "Circuit Arrangement For Operating A Semiconductor Memory System", granted May 16, 1978 to H. H. Berger et al.] The load elements of the flip-flops are highly resistive resistors or transistors switched as current sources. The read/write cycles of the storage cells are performed in several phases, and the cells are selected in response to level changes on word and bit lines. For increasing the read or the write speed and for reducing the power dissipation, the bit lines are discharged to ground by the conductive storage cell transistors. During the read phase of the store, the bit lines are charged only slightly, so that the charging current flowing through the storage cell is very low.
In recent years there has been a brisk development in the field of logic circuits and integrated semiconductor technology with bipolar transistors, which under the term MTL (Merged Transistor Logic) or IIL (Integrated Injection Logic) has become well known in the literature. Attention is drawn to the articles in IEEE Journal of Solid State Circuits, Vol. SC/7, No. 5, October 1972, page 340 and subsequent pages. Relevant solutions have also become known from U.S. Pat. Nos. 3,736,477 and 3,816,758. Reference is made to the following prior art patents and publications, at least a number of which relate to I.sup.2 L type memory circuitry. It is to be appreciated with reference to the subject invention, that the following art is not necessarily the only prior art, the best prior art, or the most pertinent prior art.
U.S. Pat. No. 3,643,231 entitled "Monolithic Associative Memory Cell" granted Feb. 15, 1972 to F. H. Lohrey and S. K. Wiedmann, and of common assignee herewith.
U.S. Pat. No. 3,736,477 entitled "Monolithic Semiconductor Circuit Concept of High Packing Density" granted May 29, 1973 to H. H. Berger and S. K. Wiedmann and of common assignee herewith.
U.S. Pat. No. 3,815,106 entitled "Flip-Flop Memory Cell Arrangement" granted June 4, 1979 to S. K. Wiedmann, and of common assignee herewith.
U.S. Pat. No. 3,816,758 entitled "Digital Logic Circuit" granted June 11, 1974 to H. H. Berger and S. K. Wiedmann, and of common assignee herewith.
U.S. Pat. No. 3,886,531 entitled "Schottky Loaded Emitter Coupled Memory Cell For Random Access Memory" granted May 27, 1975 to J. L. McNeill.
U.S. Pat. No. 3,993,918 entitled "Integrated Circuits" granted Nov. 23, 1976 to A. W. Sinclair.
U.S. Pat. No. 4,021,786 entitled "Memory Cell Circuit and Semiconductor Structure Therefore" granted May 3, 1977 to H. W. Peterson.
U.S. Pat. No. 4,090,255 entitled "Circuit Arrangement For Operating a Semiconductor Memory System" granted May 16, 1978 to H. H. Berger et al., and of common assignee herewith.
IBM Technical Disclosure Bulletin publication entitled "MTL Storage Cell" by S. K. Wiedmann, Vol. 21, No. 1 June 1978, pages 231-2.
"Merged-Transistor Logic (MTL)--A Low-Cost Bipolar Logic Concept" by Horst H. Berger and Siegfried K. Wiedmann, IEEE Journal of Solid-State Circuits, Vol. SC-7, No. 5, Oct. 1972, pages 340-6.
"Integrated Injection Logic: A New Approach to LSI" By Kees Hart and Arie Slob, IEEE Journal of Solid-State Circuits, Vol. SC-7, No. 5, October 1972, pages 346-51.
From U.S. Pat. No. 4,090,255 a method and a circuit arrangement for driving an integrated semiconductor storage are known, the storage cells of which consist of flip-flops with bopolar transistors and Schottky diodes as read/write coupling elements and the load elements of which are high-ohmic current sources. The read/write cycles of the storage cells, which are performed in several phases, are selected by level changes on the word and bit lines. For increasing the read and write speed as well as for reducing the power dissipation, the bit lines are discharged via the conductive storage cell transistors. Discharging of the bit lines via these conductive storage cell transistors is effected to ground. During the read phase of the storage, the bit lines are only slightly recharged, so that the recharge current flowing through the storage cell is very low.
In the past few years, there have been many developments in the field of logic arrays and integrated semiconductor storage technology with bipolar transistors, which are referred to as MTL (Merged Transistor Logic) or I.sup.2 L (Integrated Injection Logic) in the literature. In this connection, attention is drawn, for example, to articles in the IEEE Journal of Solid State Circuits, Vol. SC/7, No. 5, October 1972, pp. 340 ff. and 346 ff. Corresponding proposals are also contained in U.S. Pat. No. 3,736,477 as well as U.S. Pat. No. 3,816,748.
These concepts with bipolar transistors have short switching times and are particularly suitable for extremely highly integrated storages and logic circuit groups.
Store with storage cells of bipolar transistors having a structure resembling that of MTLs necessitate a recharging of bit data and/or control line capacitances for selecting a storage cell. For this purpose, the voltage swing of the bit lines approximately corresponds to the voltage swing of the selected word lines. As previously described in U.S. Pat. No. 4,090,255, the capacitive discharge currents are discharged to ground via the storage cells of the selected word line and via the word line driver. With a greater number of storage cells in a matrix this has the disadvantage that the area requirements of the driver switching circuits, the power dissipation for each driver, and the delay period occurring during the selection of the word line increase disproportionately, so that the advantages of the MTL structure employed would be eliminated.
To avoid this disadvantage, German Offenlegungsschrift No. 28 55 866 proposes a method of driving a semiconductor storage and a circuit arrangement. [German Offenlegungsschrift No. 28 55 866 corresponds to U.S. Pat. No. 4,280,021, entitled "Method and Circuit Arrangement for Controlling An Integrated Semiconductor Memory" filed Dec. 7, 1979 by Klaus Heuber and Siegfried Kurt Wiedmann, and granted July 21, 1981.] This method is characterized in that in due time piror to selection, a control arrangement known per se generates control signals for the storage matrix as a function of a selection signal. These control signals are simultaneously applied to a discharge circuit, common to all storage cells, and to switching transistors which are thus switched on. As a result, the discharge currents of the line capacitances on the bit data and control lines flow through the switching transistors, being jointly discharged via the discharge circuit. This circuit arrangement is characterized in that the bit lines within the storage matrix are connected to a discharge line which, in turn, is connected to a discharge circuit, and that for control purposes, the discharge circuit and all word and/or bit line switching transistors are connected via lines to a control logic controlled by the selection signal of the storage chip.
Semiconductor stores with cells of bipolar transistors have a structure similar to that of MTL and necessitate charging the bit data and/or control line capacities for storage cell selection. The voltage swing of the bit line capacities approximately corresponds to that of the selected word lines. As previously described, the capacitive discharge currents are discharged to ground through the storage cells of the selected word line and the word line driver. With a large number of storage cells in an array this has the disadvantage that the area requirements of the driver circuits, the power dissipation of each driver and the delay time during word line selection become excessive, eliminating the advantages of the MTL structure used. Therefore, German Pat. No. 29 26 050 describes a method of and a circuit arrangement for reading and writing an integrated semiconductor storage, whose storage cells consist of flip-flops with bipolar transistors in MTL technology, wherein for or during a read or write operation line capacities are discharged and a read/write circuit is provided, wherein the current required for reading and/or writing the storage cells is generated by discharging only the input capacities of the non-selected storage cells and directly applied to the selected storage cells for reading and/or writing. For this purpose, in particular the discharge currents of the bit line capacities are used for reading and/or writing a selected storage cell. The discharge currents from the bit line and injector junction capacities of the selected storage cell charge the injector diffusion capacities, and these diffusion capacities are discharged much more rapidly on the OFF than on the ON side, so that the read signal is the difference signal resulting from discharging the capacities on the output and the input side at different speeds. [German Patent 29 26 050 corresponds to U.S. Pat. No. 4,330,853 entitled "Method of And Circuit Arrangement For Reading And/Or Writing An Integrated Semiconductor Storage With Storage Cells in MTL(I.sup.2 L) Technology" granted May 18, 1982 to H. H. Heimeier et al.]
However, this read scheme (U.S. Pat. No. 4,330,853) has the disadvantage that the read signal thus obtained is not an optimum one, as charging of the bit line PNP transistors is not controlled.